The present invention relates to a signal wiring system and a jitter suppression circuit.
A jitter suppression circuit of the related art is disclosed for example in Japanese Unexamined Patent Application Publication No. 2001-344040 and Japanese Unexamined Patent Application Publication No. Hei6(1994)-53947.
The technology described in Japanese Unexamined Patent Application Publication No. 2001-344040 discloses a jitter eliminator shaping circuit 10 comprised of a band-pass filter 12 and a shaping circuit 13. The band-pass filter 12 passes only fundamental clock frequency components from the fundamental clock signal including jitter input from the input terminal 11. The shaping circuit 13 makes a voltage comparison of the output signal from a band-pass filter 12 in a comparator, and reproduces and outputs the fundamental clock (pulse).
The technology described in Japanese Unexamined Patent Application Publication No. Hei6(1994)-53947 discloses a jitter suppression circuit 20 comprised of a jitter component detector circuit 22, a variable amplifier 23, a differential amplifier 24, and a clock recovery circuit 25. The jitter component detector circuit 22 extracts just the jitter component from the clock signal containing the jitter component from the input terminal 21. The variable amplifier 23 sets an extracted jitter component amplitude that is smaller than the clock signal amplitude. The differential amplifier 24 generates a differential signal whose phase is corrected (offset) versus the jitter phase by utilizing the difference between the clock signal and the variable amplifier output, and outputs that differential signal. The clock recovery circuit 25 outputs the recovered clock signal to the output terminal based on a zero cross-point of the differential signal as a time reference.